Switching regulators typically switch at frequencies from 100 kHz-5 MHz. One common type of switching regulator is a current mode (CM) regulator. In a CM regulator there is a fast current loop that detects a ramping current through a power switch or through the inductor and a much slower voltage loop that detects the output voltage. A large capacitor connected to the output of the regulator smooths the output voltage.
When there is a load current transient, such as when the load goes into or comes out of a standby mode, the load current may instantaneously change. If, for example, the load comes out of a standby mode, the instantaneous increase in current will draw charge from the output capacitor and cause the output voltage to temporarily droop until the next switching cycle. During the next switching cycle, the regulator detects the lowered output voltage and increases the duty cycle of the power switch to compensate for the increased load current. Correcting for the current transient is a function of the voltage feedback loop bandwidth and thus takes many clock cycles, resulting in output voltage ripple.
Such ripple may cause the regulated voltage to transition out of the desired operating range. What is needed is a technique for reducing output voltage ripple in regulators due to load current transients without significantly increasing the load capacitance.
Additionally, some applications require the switching regulator to make a step change in its regulated voltage level in response to an external command signal. Once the externally generated command signal is received, a change is made to the feedback voltage or reference voltage in the relatively slow voltage loop to cause the regulator to output the new voltage. In a typical regulator, the regulator adjusts its duty cycle to match the feedback voltage to the reference voltage applied to an error amplifier. Changing the feedback voltage (to change the regulated voltage) may be by changing the resistor ratio in a resistor divider connected between the output voltage and the input into the error amplifier. However, changing the reference voltage into the error amplifier is deemed to be a simpler way to change the regulated output voltage. Other ways to change the feedback voltage may be used; however, all such changes are performed in the relatively slow voltage loop. Due to the slow reaction time of the voltage loop, there is a delay, such as on the order of 30 μS or more for only a 0.1 volt step, before the regulator outputs the new regulated voltage. The delay occurs whether the voltage step is in the positive or negative direction. In an optimal design, the voltage loop bandwidth cannot be increased without adversely impacting the phase margin.
What is needed is a technique for reducing the delay before the regulator outputs a target regulated voltage in response to an external command signal for changing the regulated output voltage.